I2C - Inter Integrated Circuit (Serial Communication)

I2C Parport

2007-09-21T00:47:00.000-07:00

What's this?

This simple device allows you to connect I2C-enabled chips (serial memories, RTCs, port expanders) to your computer using printer port (LPT, parport).

Okay, but what can I use it for?

Mostly servicing stuff, like:

reading/writing serial eeproms (like 24C04 or SPD)
getting lots of GPIO, via expanders like PCF8574

Documentation

schematics [png, 18k], photo [jpg, 80k]

All pull-ups are 10-20k. The photo shows the adapter with a 24C04 EEPROM inserted (used to store HDD encryption password).

Drivers

All the needed drivers are included in 2.6 kernels. They are loaded using modprobe i2c-parport type=0. Pinout of the adapter is Philips adapter, and is also compatible with MCS Flashprogrammer. Devices can be accessed using standard /dev/i2c-* nodes or with additional drivers (modprobe pcf8574, modprobe eeprom).

I2C-Tiny-USB

2007-09-21T00:23:00.000-07:00

Fonte: Till Harbaum, I2C-Tiny-USB

Part placement

Top (click for 600 dpi)

Bottom (click for 600 dpi)

The final PCB

Interface I2C

2007-09-21T00:00:00.001-07:00

Fonte: Basicavr.com

I2C Hardware

2007-09-20T23:54:00.000-07:00

Fonte: Cubic.org

DMX4Linux can control the tda8444 DAC connected to an I2C bus. Up to 4 tda8444 can be controlled over a single I2C bus, resulting in 32 analog outputs.

If you don't have a I2C bus, you can fake it with a standard parallel port and the following schematic. Use the i2c-simple-par driver to access it.

Using your setup

You should connect your tda8444 hardware to an I2C bus and configure your Linux Kernel to enable the I2C subsystem and your local I2C device. If you are using the above parport hack, load the driver with: modprobe i2c-simple-par.

Then load the tda8444 driver: modprobe tda8444.
Finally load the DMX4Linux I2C driver: modprobe dmxi2c.
You should now have a working DMX4Linux setup.

Driver configuration

i2c-simple-par

Synopsis

i2c-simple-par [parport=]
You can use the following line in /etc/modules.conf to set another default parport.
options i2c-simple-par parport=3

dmxi2c

Synopsis

dmxi2c [adapter=]
The adapter parameter selects the 'nth DAC on the I2C bus.

Emulation des I2C-Busses per Software (16F628)

2007-09-20T23:40:00.000-07:00

Fonte: SPRUR.de

Verdrahtung

Zur Ansteuerung des I2C-Busses benötigt man 2 open-drain- oder open-kollektor-Ausgänge, die auch als Eingänge funktionieren. Das Pin RA4 ist das einzige Pin, das diese Voraussetzung erfüllt. Allerdings ist es aufgrund der RA4-Falle, nicht ganz einfach zu nutzen.
Ich bastle mir lieber aus jeweils 2 Pins des Ports A einen bidirektionalen open-drain-Leitungstreiber. Folglich sind die Pins RA0..RA3 für den I2C-Bus reserviert.

RA0 SDA-Ausgang
RA1 SCL-Eingang
RA2 SDA-Eingang
RA3 SCL-Ausgang

Die nebenstehende Grafik zeigt das an einem praktischen Beispiel.

Ich lege per #define-Befehl eingängige Namen für diese 4 Pins fest:

list p=16f628
;**************************************************************
;* Pinbelegung
;* ----------------------------------
;* PORTA: 0 SDA out
;* 1 CLK in
;* 2 SDA in
;* 3 CLK out
;* 4 -
;**************************************************************
;
;sprut (zero) Bredendiek 12/2002
; I2C-Bus am 16F628
; Prozessor 16F628
; Prozessor-Takt 10 MHz
;
; I2C am PortA
;
;**********************************************************
; Includedatei für den 16F628 einbinden
#include

; Configuration festlegen:
; Power on Timer, kein Watchdog, HS-Oscillator, kein Brown out, kein LV-programming
__CONFIG _PWRTE_ON & _WDT_OFF & _HS_OSC & _BODEN_OFF & _LVP_OFF

; für I2C
#define SDAo PORTA,0 ;Daten output
#define SDAi PORTA,2 ;Daten input
#define SCL PORTA,3 ;Takt
#define SCLo PORTA,3 ;Takt
#define SCLi PORTA,1 ;Takt input

Initialisierung

Um die Pins RA0..RA3 wie oben beschrieben nutzen zu können, müssen RA0 und RA3 als Output definiert werden. Außerdem müssen die Komparatoreingänge deaktiviert werden, damit die Pins überhaupt als digitale I/O-Pins nutzbar sind.

; Das Programm beginnt mit der Initialisierung
Init bsf STATUS, RP0 ; Bank 1
movlw B'11100110' ; PortA alle input außer RA0,3,4
movwf TRISA
bcf STATUS, RP0 ; Bank 0
clrf PORTA

; 16F628 alle Comparatoreingänge auf Digital umschalten
BSF CMCON, CM0
BSF CMCON, CM1
BSF CMCON, CM2

call i2c_reset

Einstellung der Busgeschwindigkeit

Da das gesamte Busprotokoll per Software erzeugt wird, hängt die Busgeschwindigkeit von der Kompaktheit der Softwareroutinen und dem Takt des PICs ab. Die hier vorgestellten Routinen erreichen bei 10 MHz-PIC-Takt einen I2C-Bus-Takt von 210 kHz. Sie können für low-speed-I2C-Slaves verwendet werden, wenn der PIC mit 4 MHz getaktet wird:

PIC-Takt	I2C-Takt	Standart-Mode (100 kHz)	Fast-Mode (400 kHz)
4 MHz	85 kHz	o.k.	o.k.
8 MHz	170 kHz	-	o.k.
10 MHz	210 kHz	-	o.k.
12 MHz	250 kHz	-	o.k.
16 MHz	340 kHz	-	o.k.
20 MHz	420 kHz	-	-

Natürlich kann der I2C-Takt auch durch das Einfügen einiger NOP-Befehle in die Routinen verringert werden. Eine Beschleunigung ist aber nur möglich, wenn man nicht alle Feinheiten des I2C-Busses nutzen will. Meine Routinen berücksichtigen die Möglichkeit, dass ein Slave den I2C-Takt aktiv verlängert. Das macht aber in Wirklichkeit kaum ein I2C-Schaltkreis. Wer sich sicher ist, dass er dieses Feature nicht braucht, kann die I2C-Routinen verschlanken, und einen schnelleren I2C-Takt erreichen.

Daten auf den I2C-Bus schreiben

Um Daten auf den I2C-Bus zu schreiben, wird der Bus mit i2c_on übernommen. Danach wird das zu schreibende Byte nach 'w' geladen, und danach i2c_txt aufgerufen.
Ist der Datentransfer beendet, gibt man mit i2c_off den Bus wieder frei.

Nachfolgendes Beispiel steuert einenTDA8444 an. Dieser Chip enthält acht 6-Bit-Digital-Analog-Wandler (DAC). Die ersten 6 DACs des TDA8444 werden auf 6 unterschiedliche Spannungen eingestellt:

; Achtung PIC-Takt maximal 4 MHz

call i2c_on ; Bus übernehmen

movlw H'40' ; Adresse des TDA8444 (A0..A2=0)
call i2c_tx

movlw H'00' ; kanal 0 increment adress
call i2c_tx

movlw H'00' ; DAC0: 0V
call i2c_tx

movlw H'01' ; DAC1: 1/64 Vcc
call i2c_tx

movlw H'02' ; DAC2: 1/32 Vcc
call i2c_tx

movlw H'04' ; DAC3: 1/16 Vcc
call i2c_tx

movlw H'08' ; DAC4: 1/8 Vcc
call i2c_tx

movlw H'10' ; DAC5: 1/4 Vcc
call i2c_tx

movlw H'20' ; DAC6: 1/2 Vcc
call i2c_tx

call i2c_off ; Bus freigeben

Da der TDA8444 ein Standard-Mode-Chip (max. 100 kHz) ist, darf der PIC dabei mit nur 4 MHz getaktet werden. Der TDA benötigt offiziell eine Betriebsspannung (Vcc) von mindestens 4,5V. Meiner Erfahrung nach läuft er aber erst ab 6V. Diese Betriebsspannung darf natürlich nicht mit dem Vcc-Pin des PIC verbunden werden. Der braucht seine eigenen 5 V.

Daten vom I2C-Bus lesen

Um Daten vom den I2C-Bus zu lesen, wird der Bus mit i2c_on übernommen. Danach wird die Adresse des auszulesenden I2C-Bausteins mit gesetztem Bit0 in 'w' geladen, und dieser Baustein dann mit i2c_tx adressiert. Danach wird i2c_rx oder i2c_rxack aufgerufen. Diese Routine liest ein Byte vom I2C-Bus, und schreibt es nach 'w'. i2c_rxack erzeugt zusätzlich ein ACK-Signal für den gelesenen I2C-Baustein. Das ist nötig, wenn noch weitere Bytes gelsesen werden sollen..
Ist der Datentransfer beendet, gibt man mit i2c_off den Bus wieder frei.

Nachfolgendes Beispiel steuert einen LM75-Temperatursensor an, und liest die von ihm gemessene Temperatur aus (2 Byte) :

call i2c_on ; Bus aktiv

movlw H'91' ; 1001 0001 , LM75 (A0..A2=0)
call i2c_tx ; LM75 zum Lesen adressieren

call i2c_rxack ; lesen mit ACK
movwf Temp_h ; 1. Byte in Speicherzelle Datenpuffer retten

call i2c_rx ; lesen ohne ACK - letztes Byte
movwf Temp_l ; 2. Byte in Speicherzelle Datenpuffer retten

call i2c_off ; Bus freigeben

Hilfsroutinen

Folgende Routinen werden benötigt:

i2c_reset
bringt den I2C-Bus in einen definierten Ausgangszustand
i2c_on
übernimmt den I2C-Bus, sobald er frei ist
i2c_off
gibt den I2C-Bus wieder frei
i2c_tx
sendet das Byte aus 'w' über den I2C-Bus
i2c_rx
empfängt ein Byte aus dem I2C-Bus, und legt es in 'w', buf ab
i2c_rxack
empfängt ein Byte aus dem I2C-Bus, und legt es in 'w', buf ab
anschließend wird ein ACK-Signal erzeugt

Es wird ein Register 'buf' benötigt, das mit einem EQU-Befehl vorab definiert werden muß.

;*****************************************************************
; Routinen für I2C
; Bus zurücksetzen i2c_reset
; Bus übernehmen i2c_on
; W senden i2c_tx
; Byte empfangen i2c_rx (nach w und buf)
; Byte empfangen & ACK i2c_rxack (nach w und buf)
; Bus freigeben i2c_off
;*****************************************************************
i2c_reset
bsf SDAo
bsf SCLo
nop
movlw 9
movwf buf
i2c_reset1
nop
bcf SCLo
nop
nop
nop
nop
nop
bsf SCLo
nop
decfsz buf, f
goto i2c_reset1
nop
call i2c_on
nop
bsf SCLo
nop
nop
bcf SCLo
nop
call i2c_off
return

i2c_on
; wenn SDA und SCL beide High, dann SDA auf Low ziehen
bsf SCL ; failsave
bsf SDAo ; failsave
;testen, ob der Bus frei ist
btfss SCLi
goto i2c_on ; Taktleitung frei?
btfss SDAi
goto i2c_on ; Datenleitung frei?
bcf SDAo
nop
bcf SCL
return

i2c_tx
; w über i2c senden
; takt ist unten
; daten sind unten
call WrI2cW ; 8 Bit aus W nach I2C
; ACK muß nun empfangen werden
; Takt ist low
bsf SDAo ;Datenleitung loslassen
bsf SCL ; ACK Takt high
i2c_tx2
btfss SCLi
goto i2c_tx2
nop
;i2c_tx1
; btfsc SDAi ; ACK empfangen?
; goto i2c_tx1 ; nein SDA ist high
bcf SCL ; ja , Takt beenden
bcf SDAo
return

i2c_rxack
; takt ist unten
; daten sind unten
call RdI2cW ; 8 von I2C nach W
; Takt ist unten
; ACK muß nun gesendet werden
bcf SDAo
nop
nop
nop
nop
bsf SCL
i2c_rxack1
btfss SCLi
goto i2c_rxack1
nop
bcf SCL
bcf SDAo
return

i2c_rx
; takt ist unten
; daten sind unten
call RdI2cW ; 8 von I2C nach W
; Takt ist unten
; kein ACK
nop
nop
bsf SDAo
nop
bsf SCL
i2c_rx1
btfss SCLi
goto i2c_rx1
nop
bcf SCL
bcf SDAo
return

i2c_off
; SCL ist Low und SDA ist Low
nop
nop
bsf SCL
nop
bsf SDAo
return

;*****************************************************
; I2C-Peride ist 2,5 µs
; PIC-Zyklus ist 4/10MHz = 0,4µs
; -> Takt muß für 3 Zyklen H und für 3 Zyklen L sein
; + 1 Zyklus Reserve

;schiebt das Byte aus W in den I2C
; MSB zuerst
; 78 Takte
WrI2cW
; Takt unten, Daten unten
; Datenbyte in w
movwf buf
movlw 8
movwf count ; 8 Bits
WrI2cW1
; Datenleitung setzen
bcf SDAo
rlf buf,f
btfsc STATUS,C ; 0?
bsf SDAo ; nein, 1
nop
bsf SCL ; Taht high
WrI2cW2
btfss SCLi
goto WrI2cW2
bcf SCL ; Takt low
decfsz count,f ; 8 Bits raus?
goto WrI2cW1 ; nein
return ; ja

;liest das Byte aus I2C nach W
; takt ist unten
; daten sind unten
RdI2cW
clrf buf
movlw 8
movwf count
bsf SDAo ;failsave
RdI2cW1
nop
clrc
btfsc SDAi
setc
rlf buf,f
bsf SCL ; Takt high
RdI2cW2
btfss SCLi
goto RdI2cW2
bcf SCL ; Takt low
decfsz count,f ; 8 Bits drinn?
goto RdI2cW1 ; nein
movfw buf ; ja fertig
return

A single master I2C tutorial

2007-09-20T23:34:00.000-07:00

Fonte: Best Microcontroller Projects

This I2C tutorial shows you how the I2C protocol works at the physical bit level. It only discusses single master mode (a single controlling device) as this is the most common use for I2C in a small system.

I²C (pronounced I-squared-C) created by Philips Semiconductors and commonly written as 'I2C' stands for Inter-Integrated Circuit and allows communication of data between I2C devices over two wires. It sends information serially using one line for data (SDA) and one for clock (SCL).

Note: You can find Master mode soft I2C routines in the RTC project.

Master and slave

The phillips I2C protocol defines the concept of master and slave devices. A master device is simply the device that is in charge of the bus at the present time and this device controls the clock and generates START and STOP signals. Slaves simply listen to the bus and act on controls and data that they are sent.

The master can send data to a slave or receive data from a slave - slaves do not transfer data between themselves.

Multi Master

Multi master operation is a more complex use of I2C that lets you have different controlling devices on the same bus. You only need to use this mode if you have more than one microcontroller on the bus (and you want either of them to be the bus master).

Multi master operation involves arbitration of the bus (where a master has to fight to get control of the bus) and clock synchronisation (each may a use a different clock e.g. because of separate crystal clocks for each micro).

Note: Multi master is not covered in this I2C tutorial as the more common use of I2C is to use a single bus master to control peripheral devices e.g. serial memory, ADC, RTC etc.

Data and Clock

The I2C interface uses two bi-directional lines meaning that any device could drive either line. In a single master system the master device drives the clock most of the time - the master is in charge of the clock but slaves can influence it to slow it down (See Slow Peripherals below).

The two wires must be driven as open collector/drain outputs and must be pulled high using one resistor each - this implements a 'wired AND function' - any device pulling the wire low causes all devices to see a low logic value - for high logic value all devices must stop driving the wire.

Note : If you use I2C you can not put any other (non I2C) devices on the bus as both lines are used as clock at some point (generation of START and STOP bits toggles the data line). So you can not do something clever such as keeping the clock line inactive and use the data line as a button press detector (to save pins).

You will often will find devices that you realise are I2C compatible but they are labelled as using a '2 wire interface'. The manufacturer is avoiding paying royalties by not using the words 'I2C'!

There are two wires (three if you include ground!) :

I2C Turorial: Signals definition

SDA : Serial Data
SCL : Serial Clock

I2C Turorial: end of signal definition

I2C Tutorial : Typical SDA and SCL signals

Speed

Standard clock speeds are 100kHz and 10kHz but the standard lets you use clock speeds from zero to 100kHz and a fast mode is also available (400kHz - Fast-mode). An even higher speed (3.4MHz - High-speed mode) for more demanding applications - The mid range PIC won't be up this mode yet!

Note that the low-speed mode has been omitted (10kHz) as the standard now specifies the basic system operating from 0 to 100kHz.

Slow peripherals

A slow slave device may need to stop the bus while it gathers data or services an interrupt etc. It can do this while holding the clock line (SCL) low forcing the master into the wait state. The master must then wait until SCL is released before proceeding.

Data transfer sequence

A basic Master to slave read or write sequence for I2C follows the following order:

I2C Tutorial : I2C basic command sequence.

1. Send the START bit (S).
2. Send the slave address (ADDR).
3. Send the Read(R)-1 / Write(W)-0 bit.
4. Wait for/Send an acknowledge bit (A).
5. Send/Receive the data byte (8 bits) (DATA).
6. Expect/Send acknowledge bit (A).
7. Send the STOP bit (P).

I2C Tutorial : end of I2C basic command sequence.

Note: You can use 7 bit or 10 bit addresses.

The sequence 5 and 6 can be repeated so that a multibyte block can be read or written.

Data Transfer from master to slave

I2C Tutorial : Instruction sequence data from master to slave

A master device sends the sequence S ADDR W and then waits for an acknowledge bit (A) from the slave which the slave will only generate if its internal address matches the value sent by the master. If this happens then the master sends DATA and waits for acknowledge (A) from the slave. The master completes the byte transfer by generating a stop bit (P) (or repeated start).

Data transfer from slave to master

I2C Tutorial : Instruction sequence data from slave to master

A similar process happens when a master reads from the slave but in this case, instead of W, R is sent. After the data is transmitted from the slave to the master the master sends the acknowledge (A). If instead the master does not want any more data it must send a not-acknowledge which indicates to the slave that it should release the bus. This lets the master send the STOP or repeated START signal.

Device addresses

Each device you use on the I2C bus must have a unique address. For some devices e.g. serial memory you can set the lower address bits using input pins on the device others have a fixed internal address setting e.g. a real time clock DS1307. You can put several memory devices on the same IC bus by using a different address for each.

Note: The maximum number of devices is limited by the number of available addresses and by the total bus capacitance (maximum 400pF).

General call

The general call address is a reserved address which when output by the bus master should address all devices which should respond with an acknowledge.Its value is 0000000 (7 bits) and written by the master 0000000W. If a device does not need data from the general call it does not need to respond to it.

I2C Tutorial : Reserved addresses.

0000 000 1 START byte - for slow micros without I2C h/w
0000 001 X CBUS address - a different bus protocol
0000 010 X Reserved for different bus format
0000 011 X Reserved for future purposes
0000 1XX X Hs-mode master code
1111 1XX X Reserved for future purposes
1111 0XX X 10-bit slave addressing

I2C Tutorial : End of reserved addresses.

Most of these are not that useful for PIC microcontrollers except perhaps the START byte and 10 bit addressing.

START (S) and STOP (P) bits

START (S) and STOP (P) bits are unique signals that can be generated on the bus but only by a bus master.

Reception of a START bit by an I2C slave device resets its internal bus logic. This can be done at any time so you can force a restart if anything goes wrong even in the middle of communication.

START and STOP bits are defined as rising or falling edges on the data line while the clock line is kept high.

I2C Tutorial : text definition of START and STOP signals

START condition (S)	SCL = 1, SDA falling edge
STOP condition (P)	SCL = 1, SDA rising edge

I2C Tutorial : end of text definition of START and STOP signals

The following diagram shows the above information graphically - these are the signals you would see on the I2C bus.

I2C Tutorial : end of definition of START and STOP signals

I2C Tutorial : START (S) and STOP (P) bits.

I2C Tutorial : end of definition of START and STOP signals

Note : In a single master system the only difference between a slave and a master is the master's ability to generate START and STOP bits. Both slave and master can control SDA and SCL.

Repeated START (Sr)

This seems like a confusing term at first as you ask yourself why bother with it as it is functionally identical to the sequence :

S ADDR (R/W) DATA A P

The only difference is that for a repeated start you can repeat the sequence starting from the stop bit (replacing the stop bit with another start bit).

S ADDR (R/W) DATA A Sr ADDR (R/W) DATA A P

and you can do this indefinitely.

Note: Reception of both S or Sr force any I2C device reset its internal bus logic so sending S or Sr is really resetting all the bus devices. This can be done at any time - it is a forced reset.

The main reason that the Sr bit exists is in a multi master configuration where the current bus master does not want to release its mastership. Using the repeated start keeps the bus busy so that no other master can grab the bus.

Because of this when used in a Single master configuration it is just a curiosity.

Data

All data blocks are composed of 8 bits. The initial block has 7 address bits followed by a direction bit (Read or Write). Following blocks have 8 data bits. Acknowledge bits are squeezed in between each block.

Each data byte is transmitted MSB first including the address byte.

To allow START and STOP bit generation by the master the data line (SDA) must not be changed while the clock (SCL) is high - it can only be changed when the clock is low.

Acknowledge

The acknowledge bit (generated by the receiving device) indicates to the transmitter that the the data transfer was ok. Note that the clock pulse for the acknowledge bit is always created by the bus master.

The acknowledge data bit is generated by either the master or slave depending on the data direction. For the master writing to a slave (W) the acknowledge is generated by the slave. For the master receiving (R) data from a slave the master generates the acknowledge bit.

I2C Tutorial : Definition of ACK bits

Acknowledge	0 volts
Not acknowledge	High volts

I2C Tutorial : End of definition of ACK bits

ACK data master --> slave

In this case the slave generates the acknowledge signal.

When a not-acknowledge is received by the bus master the transfer has failed and the master must generate a STOP or repeated START to abort the sequence.

ACK data slave --> master

In this case the master generates the acknowledge signal.

Normally the master will generate an acknowledge after it has received data but to indicate to the slave that no more data is required on the last byte transfer the master must generate a 'not-acknowledge'. This indicates to the slave that it should stop sending data. The master can then generate the STOP bit (or repeated START).

I2C Tutorial : Specifics for the 16F88

Pin configuration

To use the I2C mode in the 16F88 the SDA and SCL pins must be initialised as inputs (TRIS bit = 1) so that an open drain effect is created. By setting them as inputs they are not driving the wires and an external pull up resistor will pull the signals high.

Slave mode

The 16F88 fully implements all slave functions except general call.

The general call function does not really matter as it is quite specialised commanding all devices on the bus to use some data.

A low output is generated by driving the signal line low and changing the pin direction to an output. A high output is generated by changing the pin direction to an input so that the external resistor pulls the signal high.

In slave mode this action is done for you by the SSP module (the outputs of the register at SDA and SCL are driven low automatically - regardless of the state of the register value).

Master mode

Basically there is very limited master mode functionality.

There are two elements that are provided:

Interrupts
Pin control

16F88 Interrupts

There are two interrupts that activate on reception of either a START or STOP condition. These two interrupts are only useful in a multi master mode system where it is necessary for the non-master device to detect the start and stop conditions. So for a single master system they are of no use at all!

16F88 Pin control

Note When the SSP module is active SDA and SCL output are always set at zero regardless of the state of the register values. So all you have to do is control the port direction.

In master mode (16F88) SDA and SCL must be controlled using software.

I2C Tutorial : Specifics for 16F877A

It does it all for you!

Full master mode.
Full slave mode.
Full general call.

Note if you want a chip with full master and slave mode operation look for the MSSP module in a PIC chip e.g. 16F877A - then you won't need more software - just enough to drive the module.